In recent years, microfabrication of semiconductor elements in semiconductor integrated circuit devices has been advanced. With the advance of the microfabrication, a leakage current of a device tends to be increased. Also, despite the increase in the memory capacity, a semiconductor memory such as an SRAM provided in a semiconductor integrated circuit device for use in a mobile product such as a cellular phone is required to have a predetermined value in specifications of a leakage current in a standby state (in a memory data retaining state) or the like.
In an example of a known technology for reducing a leakage current in a standby state in an SRAM provided in a semiconductor integrated circuit device, a channel leakage of a memory cell is reduced by controlling a source potential (ARVSS) of the memory cell in an SRAM in a standby state.
Examples of the leakage current reducing technology in this type of semiconductor memory include: a technology in which, in a standby state, a predetermined voltage which is lower than a power supply voltage and with which a PN junction between an N-type well and a source of a P-channel MOSFET is not forward-biased is supplied to the N-type well in which the P-channel MOSFET of a memory cell is formed and a predetermined voltage which is higher than a ground potential and with which a PN junction between a P-type well and a source of an N-channel MOSFET is not forward-biased is supplied to the P-type well in which the N-channel MOSFET is formed (see Japanese Unexamined Patent Application Publication No. 2006-40495 (Patent Document 1)); a technology in which a source potential of a drive MOS transistor is set to be higher than a ground potential in a standby state (see Japanese Unexamined Patent Application Publication No. 2007-122814 (Patent Document 2)); and a technology in which a power supply voltage between a power supply potential and a reference potential is supplied between power supply terminals of each CMOS inverter constituting a memory cell when a word line is ON and a retainable voltage which is lower than the power supply voltage and equal to or higher than a lower-limit voltage with which data can be retained is supplied between the power supply terminals of each CMOS inverter constituting a memory cell when a word line is OFF (see Japanese Unexamined Patent Application Publication No. 2008-176829 (Patent Document 3)).